The Challenges of an Ideal Semiconductor Switch

This blog post was first published by United Silicon Carbide (UnitedSiC) which joined the Qorvo family in November 2021. UnitedSiC is a leading manufacturer of silicon carbide (SiC) power semiconductors and expands Qorvo's reach into the fast-growing markets for electric vehicles (EVs), industrial power, circuit protection, renewables and data center power.

The ideal switch with no conduction and switching losses has been dreamed of by power converter designers since the first tube 'switch-mode power supply' was designed in 1958 by IBM. On-state losses have certainly reduced across all switch technologies and with latest wide band-gap semiconductors, resistances of less than 6 milliohms are now achieved with 750V-rated parts. The technologies are not at their physical limits yet, so this value can be expected to reduce further still.

In today's high-performance power designs, edge rates (V/ns) have increased, which reduces switching losses, allowing for higher frequency, smaller magnetics and improved power density. However, these fast edge rates increase the possibility of EMI design-related issues that interact with circuit parasitics, causing unwanted oscillations and voltage spikes. With good design practices, these can be addressed using a small snubber.

High current edge rates produce voltage spikes and ringing in real circuits

So how severe is the problem? If we see 3000A/µs, which is typical of a silicon carbide switch, then just 100nH of connection or leakage inductance gives a 300V spike from the familiar E=-Ldi/dt. 100nH is just a few inches of PCB trace or a realistic figure for transformer leakage inductance, so it's typical of what would be seen, and a good oscilloscope would be needed to see the full extent of the voltage transient. The switch has no problem in seeing it though and will promptly die if it exceeds avalanche voltage energy ratings. The spike also rings with any circuit capacitance, generating a peak in measured EMI emissions.

A fix is to try to reduce circuit inductance, but this is often not a practical option. Otherwise, the switch could be heavily voltage-derated with a cost and on-resistance penalty, or the edge rates could be slowed with series gate resistance. This is a blunt instrument in that it delays the waveforms, restricting high-frequency operation by limiting duty cycle, and increases switch losses, while having little effect on the ringing.

Allowing the fast switching but attenuating the spike and damping, the ringing can be achieved with a snubber network. This might seem like a ‘brute force’ approach with memories of huge capacitors and power resistors, used with IGBTs for example, to try to reduce the effects of their large ‘tail’ current. However, it can be a very effective solution for switches such as SiC FETs. In this case, a snubber is used mainly to damp the ringing as well as limiting peak voltage and because the device capacitances are very low and the ring frequency high, only a very small snubber capacitor is needed, typically 200pF or so with a few ohms of series resistance. As expected, the resistor dissipates some power but it actually reduces turn-off losses by limiting voltage/current overlap both in hard and soft-switched applications.

There is an overall efficiency benefit with a snubber at high loads

The snubber does dissipate extra power on turn-on, so total losses E_(ON) + E_(OFF) need to be considered for a fair evaluation of the benefits. Figure 1 puts some measured values to E(TOTAL) for a 40-milliohm SiC FET operating at 40kHz with three situations considered: no snubber but 5 ohms for RG(ON) and RG(OFF), (blue line), a 200pF/10 ohms snubber with RG(ON) = 5 ohms and RG(OFF) = 0 (yellow line) and finally the green line is with no snubber, RG(ON) = 5 ohms and RG(OFF) = 0. This gives the lowest E_(TOTAL); but with excessive ringing, so it is not viable.

At high currents, there is a clear benefit using the snubber, with a reduction of about 10.9W dissipation at 40A compared with just adjustment of the gate resistor. At light loads, the snubber gives higher overall loss, but system dissipation is low under these conditions.

Figure 1: Energy savings with a small snubber

Figure 2 shows the effect of reduced ringing with the snubber.

Figure 2: Ringing is substantially reduced with a small snubber as well as reducing overall dissipation, turn-off delay time is reduced

The snubber is easy to implement

Therefore, the snubber is a good solution but is it realistic to implement? In practice, less than a watt is dissipated in the discrete snubber resistor and it can be a small surface mount part. The capacitor needs a high voltage rating, but it's a low value, so it is also physically small.

The SIC FET is close to being a perfect switch with its low conduction and dynamic losses, and with the simple addition of a small snubber, it can realize its full potential without causing excessive EMI or voltage stress problems. To make it even more 'perfect,' a SiC FET has an easy gate drive and a low-loss integral diode with very low thermal resistance to external heatsinking. What's not to like?