Don’t get hot under the collar, think about variation over temperature

This blog post was first published by United Silicon Carbide (UnitedSiC) which joined the Qorvo family in November 2021. UnitedSiC is a leading manufacturer of silicon carbide (SiC) power semiconductors and expands Qorvo's reach into the fast-growing markets for electric vehicles (EVs), industrial power, circuit protection, renewables and data center power.

SiC Cascode FET design improvements reduce costs.

When you think about it, we live in an atypical world. We often hear or use the word ‘typical’ in a way that is synonymous with ‘average’, but in statistical terms, there is guarantee of average occurring even once, so forget about it being typical.

Another interpretation of ‘typical’ is something that happens so frequently that it becomes predictable. That’s particularly true for behavioural tendencies and when we start thinking about the frequency of behaviour, we can’t avoid thinking about time.

Time is an interesting concept, not least because it never repeats. So why do we observe behaviour in terms of frequency over time? Perhaps it’s because pattern recognition is something we do very well; we’re comfortable with it and patterns that lead to ‘typical’ has become the preferred way of measuring behaviour.

This may be a mechanism we have developed in order to process the huge amounts of information we experience daily. If we were not able to categorize events as ‘typical’, albeit within flexible margins of variation, we would spend all day, every day, trying to evaluate everything we’re exposed to.

The problems come when we extend ‘typical’ to mean ‘always’, or unchanging. Surprises happen when we least expect them, it’s kind of their thing. But as engineers we don’t really like surprises, at least not in our designs, so we do all we can to avoid them. This makes it all the more ‘surprising’ that we tend to rely heavily on figures described as ‘typical’ in a data sheet.

One of the most commonly applied uses of ‘typical’ figures in data sheets is when they relate to temperature. But in doing this, we effectively have two variables that are being treated like constants. If this is understood and appreciated then it doesn’t really present a problem, because engineers will understand that they may need to adjust those figures for their own operating conditions. The real issue comes with making assumptions about how extrapolating a figure for one device can be applied to another device with similar, typical figures.

Power transistors have several crucial parameters, or Figures of Merit (FoM), such as the drain-source resistance, Rds, and switching losses, Eoss. These figures are normally provided in a datasheet but what isn’t always apparent is how these figures change with temperature. They are also influenced by the die area, which gives rise to the FoM of RdsA, or Rds with respect to area.

Of course, these figures are ‘typical’ and, typically, given for an operating temperature of 25℃. They are also derived from Rds(on) under those ‘typical’ conditions, which fails to factor in how Rds(on) changes over temperature and, more importantly, how those changes vary between architectures.

This is more apparent when we look at something like the UF3C065040K3S 650V SiC Cascode device from UnitedSiC, which is documented as having an Rds(on) of 52mΩ max (42mΩ typical) at 25℃. Comparing this against a 650V Superjunction MOSFET, with a Rds(on) of 45mΩ max (40mΩ typical) and it appears that the Superjunction device performs better in this particular FoM. However, as Figure 1 shows, over temperature the picture is very different. As we approach 150℃ the Rds(on) for the Superjunction device reaches 96mΩ, while for the SiC Cascode it is only 78mΩ. In fact, even at 175℃ the Rds(on) for the SiC device is still only 78mΩ, way below the Rds(on) of the Superjunction device.

Figure 1: The Rds(on) for SiC Cascode and Superjunction MOSFET devices

What is absolutely clear from Figure 1 is that the rate of increase in Rds(on) for the SiC Cascode device is much lower than for the Superjunction MOSFET, which is important because it is this FoM that impacts all the others, so if your application is operating at temperatures higher than 25℃ then it pays to look more closely at the way Rds(on) changes over temperature.

The relevance of this lower conduction loss is that the SiC Cascode FET will dissipate less power at higher temperatures; as much as 30% less power than the Superjunction device at 150℃. Because the amount of power dissipated will also contribute to a rise in temperature, lower dissipation losses means lower overall temperature and, therefore, an even lower Rds(on) figure. Lower Rds(on) also means the application can carry higher currents which, in the applications where these devices are used, has even more significant implications. Another positive impact of this FoM is that the die area can be kept to a minimum, which helps reduce switching and body diode losses.

The low rate of increase for Rds(on) over temperature for the SiC Cascode FET is an inherent feature of the technology, caused by the higher levels of doping used in SiC. This results in a slower decline in electron mobility which, in all semiconductor materials, increases as temperatures rise. When coupled with the other benefits this has, in terms of gate charge and other FoMs, then engineers will understand how using a SiC Cascode FET can help them make significant design improvements and reduce costs at a system level.

Datasheets give us an insight into how a device works over a range of conditions, but it is important to appreciate how they are affected by temperature and not make sweeping assumptions across different types of devices.