Getting the Most Performance from Your SiC FET

This blog post was first published by United Silicon Carbide (UnitedSiC) which joined the Qorvo family in November 2021. UnitedSiC is a leading manufacturer of silicon carbide (SiC) power semiconductors and expands Qorvo's reach into the fast-growing markets for electric vehicles (EVs), industrial power, circuit protection, renewables and data center power.

Performance is a subjective term – it can be measured in as many ways as you like, but in the world of power conversion, it comes down to two main interdependent values: efficiency and cost. It's common knowledge now that silicon as a semiconductor switch material is reaching its limits in both conduction and dynamic loss performance, so silicon carbide and gallium nitride wide band-gap technologies are increasingly considered for better performance. Better dielectric breakdown characteristics of these materials allow thinner, higher doped blocking layers with lower on-resistance, while the smaller die sizes also reduce device capacitances, reducing dynamic losses. Compared with silicon, losses are lower, but in practice, some aspects of wide band-gap devices are worse – SiC MOSFETs and GaN HEMT transistors often require tightly controlled gate drive conditions for optimum performance. There is also a range of differences compared to silicon switches that pose difficulties, such as variability and hysteresis of SiC MOSFET gate threshold and lack of avalanche rating in GaN.

SiC FETs are closer to the ideal switch

Getting closer to the ideal, practical switch isn't necessarily a huge leap – if a simple, vertical trench SiC JFET is combined with a silicon MOSFET, you get even lower normalized overall losses, an easy, non-critical gate drive and a robust part with high avalanche and short-circuit rating. The device is the SiC FET cascode and is shown in Figure 1 (right) compared with a SiC MOSFET on the left. The channel resistance Rchannel in the SiC MOSFET is replaced by the resistance of the low-voltage Si MOSFET in the SiC FET, which has much better inversion layer electron mobility and consequently lower loss. The SiC FET has a smaller comparative die area, especially with the co-packaged Si MOSFET stacked on top.

Figure 1: SiC MOSFET (left) and SiC FET (right) architecture compared

Comparison of performance in real life is best made with ‘Figures of Merit’ (FoMs) that combine contributions from conduction and switching losses in different applications for a given die size, which is important for yield per wafer and consequently, cost. Figure 2 shows a selection, comparing available 650V SiC MOSFETs with a 750V, Generation-4 SiC FET from UnitedSiC. RDS(ON) xA, or on-resistance per unit area, is a critical FoM, with a low value indicating a smaller die area and better yield per wafer for a given loss performance. Another FoM, RDS(ON)xEOSS, or the product of on-resistance and output switching energy, characterizes the trade-off between conduction and switching losses, important in hard-switching applications. FoM RDS(ON)xCOSS (tr), relating on-resistance to time-related output capacitance, indicates relative efficiency performance in high-frequency soft-switched circuits. A significant comparison is also the forward voltage drop of the integral diode. In the SiC FET, VF is the sum of the Si MOSFET body diode drop plus the JFET resistive drop in the third quadrant, the sum of which is around 1 to 1.5V. For a SiC MOSFET, this parameter figure can be more than 4V, resulting in significant conduction losses during switching dead time, in applications where current is commutated through the integral diode. On-resistance related FoMs in the figure are shown at 25°C and 125°C indicating superior performance of the SiC FET under real-life conditions.

Figure 2: FoMs compared between a SiC FET and SiC MOSFETs

3.6kW SiC FET Totem Pole PFC stage demonstrator peaks at 99.3% efficiency

Perhaps the best demonstration of the performance of SiC FETs is in a typical application – the Totem-Pole PFC stage. This circuit was long-known as a potentially high-efficiency solution to AC line rectification and power factor correction combined, but it is hard-switching at high power and silicon MOSFET technology produces unacceptable dynamic losses. SiC FETs solve the problem and a 3.6kW demonstrator by UnitedSiC shows 99.3% peak efficiency at 230VAC, helping 80+ Titanium system efficiency rating to be more easily achieved (Figure 3). Just 8W is dissipated in each of the two 18-milliohm SiC FETs in the 'fast leg' of the circuit, with silicon MOSFETs used as synchronous AC line rectifiers for the 'slow leg'. These could be replaced by silicon diodes for a lower-cost solution that still achieves 99%+ efficiency. The figure also shows results achieved with paralleled 60-milliohm SiC FETs, or a single 18-milliohm SiC FET for each of the fast leg switches.

Figure 3: Efficiency achieved in a 3.6kW TPPFC stage using SiC FETs

Simulation tool makes SiC FET selection easy

Selecting the best SiC FET part for optimum performance is made easy with the UnitedSiC 'FET-Jet' Calculator. This is a free-to-use web-based tool that allows a user to select their proposed design from a range of Rectifier, Inverter, or isolated and non-isolated DC/DC topologies. Operating specifications are then input and a device is selected from the UnitedSiC range of SiC FETs and diodes. The tool instantly calculates efficiency, component losses and their split between conduction and switching contributions, junction temperature rise and more. The effect of paralleling devices is supported and practical heatsink performance can be specified.

The results of simulation and practical examples show that SiC FETs can provide a significant performance boost to power converters. I started by saying that cost is a factor too and when system effects are considered, SiC FETs score here as well, with better efficiency and faster switching reducing size and costs of heatsinking and magnetic components for a lower total balance of system and cost of ownership.