Altium

Design Rule Verification Report

Date:		1/10/2024
Time:		3:22:18 PM
Elapsed Time:		00:00:01
Filename:		C:\Users\jq080021\OneDrive - Qorvo\DXP\DXP_2023\PA23_EVKs\PAC52400EVK1_RevA\PAC52400EVK1_RevA.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.152mm) (All),(All)	0
Clearance Constraint (Gap=0.254mm) (InNamedPolygon('AIO10') Or InNamedPolygon('U_OUT') Or InNamedPolygon('AIO32') Or InNamedPolygon('W_OUT') Or InNamedPolygon('V_OUT') Or InNamedPolygon('AIO54') Or InNamedPolygon('VIN')),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=0.203mm) (Max=2.54mm) (Preferred=0.254mm) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=0.127mm) (All)	0
Hole Size Constraint (Min=0.254mm) (Max=6.248mm) (All)	0
Hole To Hole Clearance (Gap=0.203mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All)	0
Silk to Silk (Clearance=0mm) (All),(All)	0
Net Antennae (Tolerance=1.27mm) (All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Total	0