SiC FET Design Tips
Power designers are extremely innovative and need important technical information to build the best end products. To support this process, Qorvo provides technical device and application content to help educate and support designers. By following these technical guidelines, power designers can now leverage the benefits of SiC FETs and deliver the best end-product performance possible. When you’re ready to get started, the FET-Jet Calculator can help you zero in on the perfect device for your design in just three easy steps.
RC Snubber Guidelines
An RC snubber circuit with a small R(G), or gate resistor, provides better EMI suppression with higher efficiency compared to using a high R(G) value. There is no extra gate delay time when using the snubber circuitry, and a small R(G) will better control both the turn-off V(DS) peak spike and ringing duration, while a high R(G) will damp the peak spike but result in a longer delay time. In addition, the total switching loss when using a snubber circuit is less than using high R(G), while greatly reducing E(OFF) from mid-to-full load range with only a small increase in E(ON). Efficiency will therefore improve with higher load current. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. For more SiC FET design information, including how a snubber circuit will improve overall system performance, see the links below.
Technical Resources
Waveform Control
LTspice Simulation Tips
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